MLCC DC bias calculator
Ceramic capacitors lose capacitance as DC voltage rises. A 10 µF part on a 3.3 V rail can behave like 3–4 µF. Estimate what you really have, then check it against your regulator's minimum.
Capacitor
Estimated effective capacitance
| Likely range at bias (per cap) | — |
| Capacitance retained | — |
| Worst case incl. tolerance & temperature (per cap) | — |
| Total typical (all in parallel) | — |
| Total worst case (all in parallel) | — |
Why this matters
Class II ceramics (X5R, X7R) use barium-titanate dielectrics whose permittivity drops as the electric field rises. Small packages and high capacitance per volume suffer most, because the dielectric layers are thinnest. The usual results are buck converters that ring or go unstable, LDOs that oscillate, and rails that droop under load steps, all on boards that passed ERC and DRC.
- Choose a larger package or a higher voltage rating to keep more capacitance.
- Check the regulator's minimum effective output capacitance, not the nominal value.
- C0G/NP0 parts have essentially no DC bias loss, but come in small values only.
This is an engineering estimate from a general empirical model of Class II MLCC behaviour, not data for a specific part. Real DC bias curves vary widely by manufacturer and series. For final designs, check the manufacturer's tool (for example Murata SimSurfing, TDK SEAT or Samsung's characterisation data). Aging (typically 1–3% per decade-hour for X7R/X5R) and AC ripple are not included.